1. Field of the Invention
The present invention relates to an MOS current mirror and, more particularly, to an MOS current mirror circuit which utilizes pairs of MOS transistors with differing threshold voltages, V.sub.T1 and V.sub.T2, to minimize the circuit performance restrictions related to the magnitude of the threshold voltage.
2. Description of the Prior Art
A current mirror is a type of current amplifier which provides a high impedance output current proportional to an input current. As MOS (metal-oxide-semiconductor) devices gain in popularity, the demand increases for various circuits, including current mirrors, which can be formed from MOS devices. One such MOS current mirror arrangement is disclosed in U.S. Pat. No. 4,327,321 issued to H. Suzuki et al on Apr. 27, 1982. The Suzuki et al circuit also includes a resistor in the input rail between a p-channel MOSFET and an n-channel MOSFET to minimize the output current dependency on variations in the power supply.
There are presently two conflicting trends in the design of MOS circuits. One is a trend toward MOS devices with shorter conduction channel lengths for accommodating higher signal frequencies. The other is a trend toward lower supply voltages for reducing power consumption, so that more devices may be included in a single circuit for integration on a single chip. The conflict arises in that as the devices of a current mirror have their channel lengths shortened, their transconductance rises, but their output conductance rises even faster. The resulting lower available current mirror output impedance has led to combined arrangements of two or more mirrors in which the output transistors are connected in series. These arrangements, however, require increased power supply voltage, or overhead, for obtaining increased output impedance since each of the output transistors requires sufficient drain-to-source voltage, V.sub.DS, to be biased in saturation.
One solution to this problem is the compound current mirror arrangement which includes input transistors having separate and equal conduction path currents but different conduction path geometries. U.S. Pat. No. 4,477,782 issued on Oct. 16, 1984 to the present applicant, E. J. Swanson and assigned to the assignee of the present application, discloses in detail this compound arrangement with differing conduction path geometries. Basically, the geometries of the input transistors are related to each other in such a manner that they result in gate bias voltages which optimize the V.sub.DS of the output transistors. For a dual pair combination with MOS devices, one of the input transistors has a conduction channel width-to-length ratio W/L which is at least four times that of the other input transistor device. Although useful, the circuit disclosed in U.S. Pat. No. 4,477,782 is limited in application by the value of the threshold voltage, V.sub.T, associated with the MOS devices. At the completion of a conventional manufacturing process, the threshold voltage V.sub.T of an MOS device has a magnitude of approximately 0.7 V (-0.7 V for p-channel devices and +0.7 V for n-channel devices). For the transistors to remain in saturation, the turn-on voltage of the device, V.sub.ON, must be less than V.sub.T. Insuring that V.sub.ON remains less than V.sub.T becomes a problem for low V.sub.T processing or high temperature operation.